The present invention relates to computer systems having synchronous data transfer interfaces and also to synchronous memory devices that interface with a synchronous data bus. More particularly, the present invention relates to a delay lock loop of a synchronous memory that comprises an initialization circuit for initializing the delay lock loop to a stable and reliable operating condition.
Known prior art computer systems include processors that exchange data with a variety of memory and input/output peripheral devices. Exemplary memory devices include read only memory (ROM), dynamic random access memory (DRAM), and/or static random access memory (SRAM). Exemplary input/output peripheral devices may include a keyboard, mouse, printer or video display unit. These exemplary memory and peripheral devices typically exchange data with a processor by way of a data bus.
Synchronous dynamic random access memories (SDRAMs) employ pipelined data transfers to a processor or bus for effecting data transfer rates that are comparable to the processor""s operating frequency. However, because the processor""s operating frequency might be different from that of the SDRAM, a memory controller may be required between the SDRAM and the processor for accommodating their different operating speeds.
Synch-link DRAM (SLDRAM), another known type of memory, exchanges data in packet formats, wherein packets of data are sent or received, as determined in accordance with a received command packet, directly to or from a processor and in synchronous relationship thereto. Additionally, if communicating directly with a processor, the SLDRAM may not require an intermediate memory controller.
In accordance with one such exemplary prior art SLDRAM system architecture, and method of operation, a master clock propagates from a processor to a plurality of SLDRAMs to assist system synchronization, with an aim of facilitating synchronous transfer of data between the processor and memory devices. As a part of this synchronization scheme, the master clock might be used to provide the basis for the generation or correlation of signals within the SLDRAM.
With reference to FIGS. 1 and 2, an exemplary, prior art SLDRAM, hereinafter memory 10, is coupled to a bus 12. Memory 10 includes an output latch 14 and buffer 15. Data is sent from these devices to bus 12 via output terminal 21. The memory also sends a clock signal, which corresponds to that which was used to capture data within latch 14, to a terminal 23 via delay element 13 and buffer 16. The output clock signal is provided to facilitate the transfer of data across bus 12 to other devices, e.g., such as a processor. Ideally, for these signals that are output from the memory""s output terminals, and referencing the waveforms of FIG. 2, transitions 32 of the data signal 28 coincide with the rising or falling edges 34 of the clock signal 30.
A synchronous relationship is also desired for a data signal and an accompanying clock signal when writing into the memory. Referencing FIGS. 3 and 4, a memory 10 is coupled to bus 12, which bus comprises N data lines 24 and M clock lines 26. Terminal 39 of memory 10 receives a data signal (e.g., waveform 43 of FIG. 4), which data signal is internally coupled to the data input of latch 33. Terminal 45 receives a clock signal (waveform 42 of FIG. 4) that is forwarded to the clock input 36 of data latch 33 by way of delay unit 35. Preferably, delay unit 35 provides an amount of delay Td1 that appropriately positions a rising edge of the delayed clock signal 44 to a time placement t1, relative the data signal, which time placement is coincident with the center of the data eye of the data signal 43 received at the data input of latch 33. However, the amount of delay that is required for optimal placement of the clock edge may change dependent upon design parameters of the data latch 33, such as its input capacitance, and any RC time constants associated with the delay circuit 35. In addition, the memory""s supply voltage and its operating temperature can affect the desired optimal placement of the clock edge. Further pushing these synchronization needs, increases in computer speeds are making the processing systems less tolerable of timing changes that might be effected by voltage or temperature variations. Accordingly, delay lock loops and associated vernier circuits have been used to attempt calibration, adjustment and/or compensation of these timing changes that occur over a circuit""s lifetime.
A known exemplary delay lock loop is shown as a part of memory 10 in FIG. 5. Memory 10 receives command data from data lines 24 of bus 12, at terminals 39A via command data lines 38A. Write data is received at terminal 39B via lines 38B. A system clock of clock lines 26, is received at terminal 41 by way of line 40, while the clock signal associated with the synchronous write data transfer is received at terminal 45 via line 46. The command data that is received at terminal 39A is forwarded to the data input of command latch 66 after passing through buffers 65. A command clock is presented to the latch input of command latch 66 by way of a previously programmed vernier select circuit 64. Vernier select circuit 64 comprises vernier 60 and multiplexer 62. Vernier 60 receives the command clock and provides a plurality of variously delayed representations of the command clock at the CCLK1-CCLKN outputs. Having been previously programmed in a known fashion, multiplexer 62 selects a particularly delayed representation of the clock signal for selecting an edge placement of the selected delayed clock signal that is to be substantially coincident with centers of eye patterns of the data signal received at the data input of latch 66. This delayed clock signal, which selection is routed by multiplexer 62, is forwarded as the latching clock signal to the command latch 66 for use in capturing the command data therein.
A signal from one of the outputs of vernier A, typically the output of greatest delay, e.g., CCLKN, is fed back as the variably delayed signal of the delay lock loop to variable input 70 of phase detector 72. The phase detector 72 compares the phase of the signal at variable input 70 to that of the reference signal received at reference input 74. The reference signal corresponds to the received system clock, but delayed by an amount associated with the propagation delay of buffer 73. Phase detector 72 generates an error signal at its output 75 in accordance with the detected phase difference between the variably delayed signal and the reference signal. Integrator 76 receives the error signal from phase detector 72 and generates a tune voltage (Vtune) by integrating the error signal. The tune voltage from the integrator is coupled to the control input of vernier A and is used for adjusting the amount of delay that is provided by vernier A. Upon acquiring a locked condition, the delay lock loop aims to keep the phase of the variably delayed signal at variable input 70 coincident with that of the reference clock. Thus, the delay lock loop strives to preserve the integrity of data reception by, ideally, keeping a latching edge of the selected, vernier-delayed clock signal centered within the data eye of the data signal that is received at the data input of latch 66.
When channeling command data to memory 10, the external system, e.g., a processor, supplies a continuous system clock on line 40, which runs continuously over time. On the other hand, when transferring write data that is to be written into the memory device, the clock that accompanies the write data on line 46 may be discontinuous, i.e., present only for a duration for accompanying the data transfer. Because the accompanying data clock is not continuous, a separate xe2x80x9cslavedxe2x80x9d vernier circuit 48 is configured for selecting optimally delayed representations of the data clock for latching data into respective registers of the receiving write data latches 33. xe2x80x9cSlavedxe2x80x9d vernier 48 receives the tune voltage that is generated by the continuously locked delay lock loop associated with receiving the command data. This configuration assumes, of course, that the circuitry of vernier 48 and multiplexer 52 correspond to that of vernier 60 and multiplexer 62, and that any variations with respect to voltage and temperature experienced in one will correspond substantially to that experienced by the other. Accordingly, the tune voltage adjustments generated for the one, preferably, is able to, likewise, sufficiently compensate the other for keeping the intermittent data clock appropriately positioned relative to its write data signal.
Control logic 58, as known in the art, establishes the configurations of multiplexers 52, 62 and controls operation of access circuitry 54 associated with accessing memory array 56.
To summarize, the control loop associated with the exemplary delay locked loop of FIG. 5 includes the variable input 70 of phase detector 72, integrator 76, the control input 77A of vernier A 60, and the return line to the variable input 70. It is noted, however, that for this exemplary prior art embodiment, multiplexer 62 resides outside the control loop of the delay lock loop. Accordingly, changes in the multiplexer""s operating temperature or voltage might affect its propagation delay, and likewise might adversely impact the placement of the clock signal relative to the data signal.
Addressing this shortcoming of the multiplexer, and referring to FIG. 6, the prior art provided the xe2x80x9ccompoundxe2x80x9d delay lock loop. Essentially, the compound delay lock loop comprises an outer delay lock loop wrapped around an inner delay lock loop. For the exemplary compound delay lock loop of FIG. 6, the outer delay lock loop comprises phase detector 72B, integrator 76B, VtuneB control input 79, variable delay 98, the 180xc2x0 signal path through vernier 60 (i.e., relative to the first tap Txcfx86), emulator circuit 88 and the return back to the variable input 70 of phase detector 72B. The emulator circuit 88 incorporates emulating multiplexer 90 and emulating driver 92 for emulating the delay characteristics of external multiplexer 62 and driver 61 that are external the control loop of the delay lock loop. Having the emulator circuit within the control loop allows the delay lock loop to substantially compensate for deviations of the external elements (e.g., multiplexer 62 and driver 61) by way of the delay lock loop compensating the variations of surrogate emulator circuit 88.
If the delay of the emulator circuit changes, as may be effected by a voltage or temperature change, the phase detector 72B detects a phase difference between the variable signal at variable input 70 and the reference clock at the reference input 74, and an error signal to integrator 76B responsive to the detected phase difference is generated. Depending on the direction of the phase shift, integrator 76B will ramp the tune voltage VtuneB up or down for adjusting the delay of variable delay element 98 with an aim for compensating the change in delay of the emulator circuit. For example, if the delay through the emulator circuit 88 should increase, then the control loop of the delay lock loop will attempt to decrease the delay of the variable delay element 98 to keep the phase of the variable signal substantially coincident (or xe2x80x9clockedxe2x80x9d) to that of the reference signal at the reference input 74. Likewise, if the delay through the emulator 88 should decrease, then the delay lock loop will increase the delay of the variable delay element 98.
Provided that emulator circuit 88 accurately emulates the external multiplexer 62 and driver 61 per their delay sensitivities with respect to voltage and temperature, then the outer loop""s control of the variable delay element keeps the latching transitions of the signal at the latching input of latch 66 substantially optimally positioned, thereby substantially accommodating temperature- or voltage-effected delay variations of multiplexer 62 or buffer 61.
The inner delay locked loop, further referencing FIG. 6, comprises multi-tap vernier 60, phase detector 72A and feedback circuit 76A. The feedback circuit has its output coupled to the control input 77A of vernier 60 and provides the tune voltage VtuneA for controlling the vernier""s delay. When locked, the inner delay lock loop maintains the relative phase relationships of the variously delayed signals of the vernier""s output taps, with an aim of accommodating any temperature or voltage changes that might otherwise affect vernier 60. More particularly, the inner delay lock loop ideally provides a control signal VtuneA to the control input 77A of vernier 60 for maintaining a 180xc2x0 phase difference between the signals of the vernier""s first and last output taps.
In operation, referencing the timing diagrams of FIG. 7, a system clock (CMDCLK) passes through buffer 73 (of FIG. 6) to provide signal A. Variable delay element 98 provides signal B with a delay determined in accordance with the value of the outer loop""s control signal VtuneB. Vernier 60 receives signal B and outputs progressively delayed representations C, D, etc., of signal B at taps T0, T1 . . . T15. The incremental delay between the output taps may be, in general, equal to the vernier""s total delay divided by the number of taps. The inner delay lock loop controls the delay of vernier 60 by providing a value for control signal VtuneA for maintaining a 180xc2x0 phase difference between signals C and D of the first and last taps.
As determined by the configuration signals 63, multiplexer 62 selects desired output taps of vernier 60 from which to source different internal signals of the memory. For example, the configuration signal Y1SEL less than 0:3 greater than  for a first channel configures the multiplexer to select a particular one of the 16 taps from which to source the command clock signal E for driving the latch input of command latch 66. Likewise, the configuration signal Y2SEL less than 0:3 greater than  determines the tap from which to source another clock signal F. Known calibration procedures obtain values for the configuration signals, which are determined to obtain the optimally delayed representations of the system clock for their respective application. For the application associated with the command clock signal E, the calibrated value for configuration signal Y1SEL less than 0:3 greater than  obtains an optimally delayed representation of the system clock for placing a rising edge of the derived signal E centered within (relative to) a data eye of the data signal H as received by latch 66. Similarly as discussed relative to FIG. 5, command data buffer 65 and command clock buffer 73 are designed similarly to provide similar propagation delays with similar temperature or voltage sensitivity characteristics, as portrayed by the waveforms A and H relative to CMDCLK and CMDDATA.
Further referencing FIG. 6, and as already noted, the compound delay locked loop provides the command clock for latching command data into latch 66. Emulator circuitry 88 simulates multiplexer 62 and clock driver 61 so that the outer delay lock loop can adjust the delay of the variable delay element 98 for accommodating the delay deviations of the emulated external elements to present an optimal timing relationship of the command clock signal relative to the data signal received by latch 66. In other applications, such as, for example, writing data from the memory to a bus or receiving data to be written within the memory, the delay lock loop may need to accommodate delay changes effected by voltage or temperature sensitivity characteristics of, e.g., an output driver, edge shaper, or other signal conditioning circuit. However, with the prior art delay lock loops discussed herein, the emulator circuit for emulating the multiplexer, driver, shaper and/or other conditioning circuits, because of temperature or voltage variations, may accumulate, a delay shift magnitude that exceeds an adjustment limit of variable delay element 98. This is especially true if the delay lock loop was initialized with the variable delay element set near its lower limit. Accordingly, the memory""s data transfer integrity can be compromised.
To better appreciate the problems of the prior art, one should note that a delay lock loop can lock with a delay that is an integral number of clock cycles long, i.e., the delay may be 1, 2, 3, or more cycles of the input frequency. Referring to FIG. 6, the problem to be solved arises when the delay between nodes B and G is slightly less than an integral number of clock cycles. The loop may lock with the delay of variable delay element 98 near the minimum of its range. If the temperature or supply voltage causes the delay of emulator circuit 88 to increase, variable delay 98 will then be unable to decrease, causing the loop to unlock. One solution to this problem is to run the loop at a submultiple of the clock frequency by inserting a frequency divider directly following buffer 73, and choosing the divisor such that the delay between nodes B and G is substantially less than one cycle of the divided clock. However, even with a frequency divider, a problem can also occur if the loop locks with the delay of variable delay 98 near the maximum of its range. A decrease in the delay of emulator circuit 88 will again cause the loop to unlock.
Accordingly, there exists a need to assure the integrity of data transfer for synchronous data networks and its associated synchronous memory. Additionally, there exists a need to improve the reliability and initialization of delay locked loops of such synchronous memory. The present invention recognizes these needs and proposes solutions thereto.
A method and circuitry for a delay lock loop useful in synchronizing the accessing of a memory array with a system clock is disclosed. In a preferred embodiment, the delay lock loop includes a variable delay element. The delay of the variable delay element is initially set to a minimum delay value. The system clock is then frequency divided and sent to the variable delay element, the output of which will ultimately be used to access the memory array in a synchronized manner with the system clock. The frequency divided clock and the output of the variable delay element are input to a phase detector, which creates a control signal for adjusting the delay of the variable delay element. After the signals are determined to be locked by the phase detector, an undivided clock signal version of the clock signal is sent to the variable delay element, and a frequency divided version of the output of the variable delay element is sent to the phase detector in lieu of the previous output of the variable delay element.